1. Field of the Invention
The present invention relates to a driving method of a solid-state imaging device (image sensor) for imaging an object and outputting an image signal in accordance with the image of the object, a solid-state imaging system having the solid-state imaging device and a driving unit, and a camera system. For example, the driving method, the solid-state imaging system, and the camera system are preferably used in an electronic still camera.
2. Description of the Related Art
Recently, electronic still cameras (digital still cameras) have been increasingly in widespread use. Since capturing still pictures at a high resolution is required in such electronic still cameras, mechanisms for independently outputting the signals of all pixels without mixing are adopted. For example, when CCD imaging devices are used, a so-called all-pixels readout mode or a so-called frame readout mode (refer to FIGS. 16 to 19) is employed. In the all-pixels readout mode, all pixels are read out at the same time and the signal charges of the pixels are independently output without mixing them in the vertical CCDs (vertical registers). In the frame readout mode, mechanical shutters are used and the signal charges of odd-numbered lines and even-numbered lines are alternately read out for every field and supplied to vertical CCDs to independently transfer the signal charges of pixels.
As an example of a method for increasing the data rate of the signals output from imaging devices in the capture of still images, a line decimation readout mode (refer to FIGS. 20 to 23) has been suggested. In the line decimation readout mode, since empty packets, having no signal charge, behind a packet including a signal charge Qs are mixed in the horizontal register to eliminate a period having no signal, it is necessary to perform vertical transfer corresponding to a predetermined number of lines (for example, two lines) during a horizontal blanking period. It is assumed here that the horizontal blanking period during which the vertical transfer is performed is the same in the two operation modes (the frame readout mode and the decimation readout mode) (refer to FIGS. 18 and 22). When the overlap period of the vertical transfer clocks is represented by “x”, in the line decimation readout mode, the overlap period of the vertical transfer clocks is represented by “½x” because the vertical transfer corresponding to two lines is performed, as shown in FIG. 22. Accordingly, the transfer efficiency is decreased and it is necessary to drive the vertical transfer at a speed higher than that in the frame readout mode.
However, when the vertical transfer is driven at a higher speed, a reduction in drive voltage caused by a electrode resistance or a propagation delay in drive pulses occurs at positions far from the input terminals of the vertical transfer clocks (for example, at an opposing side in one-side input, as shown in FIG. 24B, or in the center of the device in two-sides input, as shown in FIG. 24C), to produce a phenomenon including an obtuse drive waveform shown in FIG. 24A. In such a case, the transfer efficiency of the vertical CCDs is decreased and/or the amount of processed charge is decreased. A driver is omitted in FIGS. 24B and 24C.
The inventor has suggested one method for solving such problems in, for example, Japanese Unexamined Patent Application Publication No. 10-013742 (hereinafter referred to as Patent Document 1) (refer to FIGS. 25 and 26 showing the outline of this method). According to the method disclosed in Patent Document 1, as shown in FIG. 25, the vertical transfer is performed by using a combination of pairs of vertical transfer clocks having opposite phases during the vertical transfer for four-phase drive to prolong the overlap period of the vertical transfer clocks. Accordingly, even in the line decimation readout mode, it is possible to perform the vertical transfer in a state in which a longer overlap period (equal to “x” shown in FIG. 18), as in the two-field/frame readout mode, is secured to improve the transfer efficiency of the vertical CCDs.
In recent years, the cell size has been increasingly reduced for increasing the resolution (increasing the number of pixels) or for reducing the size of the device. In the frame readout mode, a three-field readout mode (refer to FIGS. 6 and 7 described below) and a four-field readout mode (refer to FIGS. 10 and 11 described below) have been come into practical use, in addition to a two-field readout mode, in related arts, in which the frame is divided into two fields for readout.
However, in a three-or-more-field frame readout mode, the overlap period is reduced to decrease the efficiency of the vertical transfer not only in the line decimation readout operation but also in the frame readout operation. For example, when the horizontal blanking period during which the vertical transfer is performed is the same as in the two-field readout mode, the overlap period of the vertical transfer clocks is represented by “x” in the two-field readout mode (FIG. 18) while the overlap period of the vertical transfer clocks is represented by “⅔x” in the three-field readout mode shown in FIGS. 27 and 28. In addition, although not shown in the figures, the overlap period of the vertical transfer clocks is represented by “¼x” in the four-field readout mode. Accordingly, a propagation delay occurs in the vertical transfer clocks and the waveform becomes obtuse, as shown in FIG. 24A, at a position far from the input terminals of the clocks. As a result, the transfer efficiency of the vertical registers is decreased and/or the amount of processed charge is decreased. The same applies to a five-or-more-field readout mode.
Although the reduced amount of processed charge in the vertical registers is relatively small in the three-or-more-field readout mode because the number of the on transfer channels in the vertical registers in the three-or-more-field readout mode is greater than that in the two-field readout mode, the transfer efficiency is decreased.
The decrease in the transfer efficiency can be inhibited by setting the transfer speed of the vertical CCDs (the overlap period of the vertical transfer clocks) as in the two-field readout mode while maintaining the frame rate by increasing the horizontal drive frequency.
However, increasing the horizontal drive frequency causes the decrease in the transfer efficiency of the horizontal CCDs. In addition, new problems including an increase in the power consumption of the horizontal CCDs, an increase in the cost of used components, and a decrease in the S/N ratio are caused as the frequency is increased. Hence, it is not preferable that the horizontal drive frequency be increased.
It is preferable that the method disclosed in Patent Document 1 be utilized. However, although the method disclosed in Patent Document 1 is effective for application to the line decimation readout mode in contradistinction to the above two-field readout mode, the method is not necessarily applicable to the drive for any number of fields or any number of phases in the three-field readout mode or a more-than-three-field (for example, a four, a five, or more-than-five-field) readout mode. This is because, for example, the method disclosed in Patent Document 1 cannot be applied to the drive for an odd number of phases owing to a basic restriction in that the vertical transfer is performed by using a combination of pairs of the vertical transfer clocks having opposite phases (complementary). The method disclosed in Patent Document 1 is not a versatile method for solving the problem of a decrease in the efficiency of the vertical transfer in various readout modes.